1. Field of the Invention
The present invention relates to an apparatus and method for synchronizing systems having different clock frequencies. Specifically, the invention relates to a synchronization system for use as part of a cursor control so as to properly present intensity data of a cursor pattern for display in correct synchronization with video data which is normally presented to a high resolution display.
2. DESCRIPTION OF THE PRIOR ART
High resolution graphic displays typically used as part of a computer system normally include a cursor which can be visually shifted to any portion of the display screen either manually or automatically. The cursor display may take a variety of patterns and a typical cursor is formed as a small arrow. The cursor pattern is provided as an overlay to the normal video data which is presented on the display screen. The location of the cursor should appear at any randomly selectable coordinate position on the display screen and the presentation of the cursor overlay pattern should be synchronized with the normal video data.
In the prior art, cursor overlay patterns have been presented directly to the video display as a separate input and not forming part of the normal video input. This type of prior art cursor display is relatively expensive since it requires completely separate hardware including the generation of clock signals in synchronism with the normal video input. This type of prior art system being separate from the generation of the video signals cannot utilize the flexibility and the advantages of new types of video display systems. An alternative way of providing cursor data is to modify the video memory to include the cursor. This degrades the performance of updating the video while there is cursor movement.
One new type of video display system incorporates a very flexible color generating system referred to as a RAMDAC.TM. which is a trademark of the assignee of the present application. This "RAMDAC" may be provided on a single IC chip and incorporates a random access memory and integral digital-to-analog converters to provide a complete color palette for the video display. This allows video input signals to be completely adjusted as to color internally within the "RAMDAC" so as to produce output video color signals of any hue or intensity completely under the control of the user of the device. Internally, the "RAMDAC" operates at a high clock speed such as 100-150 MHz. The output from the "RAMDAC" is provided at this high speed on a video coaxial line so as to be a direct input to the video display.
It is, therefore, desirable to produce an overlay signal forming cursor data directly to the "RAMDAC" through an overlay input, with this cursor data in synchronism with the video data. Since the overlay signal forming the cursor data presented to the "RAMDAC" is not at video frequency but is generally at some frequency considerably less than video frequency, such as 1/4 or 1/5 of the video frequency, the problem is to synchronize the cursor signal with the regular video signal. Typically, the data inputted to the "RAMDAC" which may be either the regular video data or the cursor data is provided in digital form as groups or blocks of data in parallel Normally, this parallel data is presented at a lower frequency or clock rate, such as 1/4 or 1/5 of the frequency of the internal clock of the "RAMDAC". Since blocks of the data are presented in parallel at the lower clock rate, this has the effect, however, of providing the data at a higher serial clock rate since, for example, five pieces of data presented in parallel at 20 or 25 MHz is equivalent to the same five pieces of data transmitted during the same time interval at 100 or 125 MHz in series.
The key problem, however, is that the synchronization of the data between different IC chips can only have clock signals at a relatively low frequency such as 20-25 MHz, but it is desirable to have the internal video clock and the output video signals of the RAMDAC operating at a much higher frequency such as 100 or 125 MHz. Using 25 MHz as an example and with a parallel block of five discrete words of data, it would be desirable to have the video clock operate at 125 MHz which represents a division of five between the two clock signals. If the video clock is 100 MHz and with a parallel block of four discrete words of data, this would represent a division of four between the two video signals. It would, therefore, be desirable to provide an apparatus and method that would allow for the synchronization of data between IC chip systems at frequencies that are a selectable submultiple of the higher clock frequency internal to one of the systems. As an example, it would be desirable to select submultiples such as 5 or 4 or actually any submultiple.